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CY7C1049CV33 4-mbit (512 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ?408-943-2600 document #: 38-05006 rev. *k revised march 02, 2011 4-mbit (512 k 8) static ram features temperature ranges ? commercial: 0 c to 70 c high speed ? t aa = 8 ns low active power ? 360 mw (max) 2.0 v data retention automatic power down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features functional description the CY7C1049CV33 is a high performance cmos static ram organized as 524,288 words by eight bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the output s are disabled (oe high), or during a write operation (ce low, and we low). the CY7C1049CV33 is available in standard 44-pin tsop ii package with center power and gr ound (revolutionary) pinout. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines . a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 13 a 14 a 15 a 16 a 17 row decoder column decoder 512k x 8 array input buffer a 10 a 11 a 12 a 18 logic block diagram [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 2 of 13 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 pin definitions .................................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ....... .......................................... 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 4 ac switching characteristics ......................................... 6 switching waveforms ...................................................... 7 truth table ........................................................................ 8 ordering information ....................................................... 9 ordering code definitions ..... ...................................... 9 package diagram ........................................................... 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design support ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 3 of 13 selection guide description -8 unit maximum access time 8ns maximum operating current 100 ma maximum cmos standby current 10 ma pin configuration figure 1. 44-pin tsop ii (top view) a 6 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 7 a 8 a 9 nc nc nc nc a 18 v ss nc a 15 a 0 a 3 i/o 0 a 4 ce a 17 a 12 a 1 a 2 18 17 20 19 i/o 1 27 28 25 26 22 21 23 24 nc v ss we i/o 2 i/o 3 a 5 nc a 16 v cc oe i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 13 a 11 a 10 nc nc nc pin definitions pin name 44-pin tsop ii pin number i/o type description a 0 ?a 18 3?7, 16?20, 26?30, 38?41 input address inputs used to select one of the address locations. i/o 0 ?i/o 7 9, 10, 13, 14, 31, 32, 35, 36 input/output bidirectional data i/o lines. used as input or output lines depending on operation. nc [1] 1, 2, 21, 22, 23, 24, 25, 42, 43, 44 no connect no connects. this pin is not connected to the die. we 15 input/control write enable input, active low. when selected low, a write is conducted. when selected high, a read is conducted. ce 8 input/control chip enable input, active low. when low, selects the chip. when high, deselects the chip. oe 37 input/control output enable, active low. controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. v ss , gnd 12, 34 ground ground for the device. should be connected to ground of the system. v cc 11, 33 power supply power supply inputs to the device. note 1. nc pins are not connected on the die. [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 4 of 13 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............................... ?65 ? c to +150 ? c ambient temperature with power applied .......................................... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [2] ?0.5 v to +4.6 vdc voltage applied to outputs in high z state [2] .................................. ?0.5 v to v cc + 0.5 v input voltage [2] .................................... ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c3.3 v ? 0.3 v electrical characteristics over the operating range parameter description test conditions -8 unit min max v oh output high voltage v cc = min; i oh = ?4.0 ma 2.4 ?v v ol output low voltage v cc = min; i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input load current gnd < v i < v c ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc ? 100 ma i sb1 automatic ce power down current ?ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max ? 40 ma i sb2 automatic ce power down current ?cmos inputs max. v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ? 10 ma capacitance tested initially and after any design or proce ss changes that may affect these parameters. parameter [3] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out i/o capacitance 8 pf thermal resistance tested initially and after any design or proce ss changes that may affect these parameters. parameter [3] description test conditions 44-pin tsop-ii unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 41.66 c/w ? jc thermal resistance (junction to case) 10.56 c/w notes 2. v il (min) = ?2.0 v and v ih (max) = v cc + 0.5 v for pulse durations of less than 20 ns. 3. tested initially and after any design or proc ess changes that may affect these parameters. [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 5 of 13 figure 2. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 30 pf * capacitive load consists of all components of the test environment (b) r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5 v (c) (a) 3.3 v output 5 pf (d) r 317 ? r2 351 ? 10-ns devices: 12-, 15-ns devices: high z characteristics: note 4. ac characteristics (except high z) for 10 ns parts are tested using the load conditions shown in figure 2 (a). all other speeds are tested using the thevenin load shown in figure 2 (b). high z characteristics are tested fo r all speeds using the test load shown in figure 2 (d). [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 6 of 13 ac switching ch aracteristics over the operating range [5] parameter description -8 unit min max read cycle t power [6] v cc (typical) to the first access 100 ? ? s t rc read cycle time 8 ?ns t aa address to data valid ? 8ns t oha data hold from address change 3 ?ns t ace ce low to data valid ? 8ns t doe oe low to data valid ? 5ns t lzoe oe low to low z 0 ?ns t hzoe oe high to high z [7, 8] ? 4ns t lzce ce low to low z [8] 3 ?ns t hzce ce high to high z [7, 8] ? 4ns t pu ce low to power up 0 ?ns t pd ce high to power down ? 8ns write cycle [9, 10] t wc write cycle time 8 ?ns t sce ce low to write end 6 ?ns t aw address setup to write end 6 ?ns t ha address hold from write end 0 ?ns t sa address setup to write start 0 ?ns t pwe we pulse width 6 ?ns t sd data setup to write end 4 ?ns t hd data hold from write end 0 ?ns t lzwe we high to low z [8] 3 ?ns t hzwe we low to high z [7, 8] ? 4ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v. 6. t power gives the minimum amount of time that th e power supply should be at stable, typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ac test loads. transition is meas ured 500 mv from steady-stat e voltage. 8. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 9. the internal write time of the memo ry is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data setup and ho ld timing should be referenced to the leading edge of the sig nal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 7 of 13 switching waveforms figure 3. read cycle no. 1 (address transition controlled) [11, 12] figure 4. read cycle no. 2 (oe controlled) [12, 13] figure 5. write cycle no. 1 (we controlled, oe high during write) [14, 15] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 16 notes 11. device is continuously selected. oe , ce = v il . 12. we is high for read cycles. 13. address valid before or similar to ce transition low. 14. data i/o is high impedance if oe = v ih . 15. if ce goes high simultaneously with we high, the output remains in high impedance state. 16. during this period, the i/os are in output state. do not apply input signals. [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 8 of 13 figure 6. write cycle no. 2 (we controlled, oe low) [17] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 18 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high z power down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) notes 17. if ce goes high simultaneously with we high, the output remains in high impedance state. 18. during this period, the i/os are in output state. do not apply input signals. [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 9 of 13 ordering information speed (ns) ordering code package diagram package type operating range 8 CY7C1049CV33-8zsxc 51-85087 44-pin tsop ii (pb-free) commercial ordering code definitions temperature range: c = commercial x = pb-free; x absent = leaded package type: zs = 44-pin tsop ii speed grade: 8 ns v33 = 3.0 v to 3.6 v process technology:c ? 150 nm data width: 8-bits 4-mbit density fast asynchronous sram marketing code: 7c = srams company id: cy = cypress cy 1 c - 8 zs x v33 c 7c 04 9 [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 10 of 13 package diagram figure 7. 44-pin tsop ii, 51-85087 51-85087 *c [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 11 of 13 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable oe output enable ram random access memory i/o input/output soj small outline j-lead ttl transistor-transistor logic tsop thin small outline package we write enable symbol unit of measure ? ohms ns nano seconds vvolts s micro seconds a micro amperes ma milli amperes mm milli meter ms milli seconds mhz mega hertz pf pico farad % percent mw milli watts wwatts c degree celcius [+] feedback
CY7C1049CV33 document #: 38-05006 rev. *k page 12 of 13 document history page document title: CY7C1049CV33 4-mbit (512 k 8) static ram document number: 38-05006 rev. ecn orig. of change submission date description of change ** 112569 hgk 03/06/02 new data sheet *a 114091 dfp 04/25/02 changed tpower unit from ns to ? s *b 116479 cea 09/16/02 add applications foot note to data sheet, page 1. *c 262949 rkf see ecn added automotive-e specs added ? ja and ? jc values on page #3. *d 300091 rkf see ecn added -20-ns speed bin *e 344595 syt see ecn added pb-free package on page #8 removed shading for CY7C1049CV33-15zsxe in the ordering information on page 9 *f 2615344 vkn/pyrs 12/03/08 added automotive-a information removed 8 ns and 20 ns speed bins, changed t power spec from 1 ? s to 100 ? s, updated ordering information table. *g 2841563 nxr/ 01/07/ 2010 added CY7C1049CV33-10vxa to ordering info table. *h 2898958 aju 03/25/10 removed inactive parts from t he ordering informaiton table. updated package diagrams. *i 2954734 aju 06/30/2010 new part number added CY7C1049CV33-10zxc to ordering info table. *j 3072834 pras 11/12/2010 removed obsolete parts and updated package diagram. *k 3185812 pras 03/02/2011 updated features . updated functional description . updated selection guide (added -8 ns speed grade devices and removed -10 ns, -12 ns, and -15 ns speed grade devices). removed figure 36-pin soj (top view) in pin configuration . updated electrical characteristics (added -8 ns speed grade devices and removed -10 ns, -12 ns, and -15 ns speed grade devices). deleted 36-pin soj column in thermal resistance . updated ac switching characteristics (added -8 ns speed grade devices and removed -10 ns, -12 ns, and -15 ns speed grade devices). added units of measure . dislodged automotive information to 001-67511. removed soj package related information in all instances in the document. [+] feedback
document #: 38-05006 rev. *k revised march 02, 2011 page 13 of 13 all products and company names mentioned in this docum ent may be the trademarks of their respective holders. CY7C1049CV33 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expect ed to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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